Synchronous static RAM (SRAM) architectures are evolving to support the high-throughput requirements of communications, networking, and digital signal processing (DSP) systems. Previous Sync SRAM ...
Memory bandwidth has been the Achilles heel of embedded communication designs, especially as line speeds move to OC-192 rates and above. To solve this problem, many embedded communication developers ...
Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
In Part 1, we reviewed the importance of simultaneous switching output (SSO) timing and the challenges associated with double data rate (DDR) simulation complexity. DDR memory interfacing has reached ...
A non-intrusive device, the FS2009 PCI-X-2.0 protocol analysis probe captures signal activity at up to 266 Mtransfers/s (133-MHz clock). It supports PCI-X 1.0 and 2.0 Mode 1 and Mode 2 ...
CHESTNUT RIDGE, N.Y., Nov. 24, 2014 /PRNewswire/ -- Teledyne LeCroy today introduces the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most ...
As memory technology evolves, there is an increasing move towards higher operating frequencies and the use of BGA (ball grid-array) chip packages. This is as true for the DDR/DDR2/DDR3 memory modules ...
Faster data processing requires faster memory. Double data rate synchronous dynamic random-access memory (DDR SDRAM) enables the world’s computers to work with the ...
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